1. Field of the Invention
The present invention generally relates to the fabrication of integrated circuits, and, more particularly, to the design of individual field effect transistor elements so as to enhance the performance thereof.
2. Description of the Related Art
Integrated circuits typically include a large number of individual circuit elements, such as transistors, capacitors, resistors and the like. These individual circuit elements are electrically connected according to the desired circuit layout by respective conductive lines, which are mainly formed in separate “wiring” layers that are typically referred to as metallization layers. For enhancing the performance of the integrated circuit, usually the number of individual circuit elements is increased, thereby obtaining a more complex functionality of the circuit, and associated therewith the feature sizes of the individual circuit elements are reduced.
Generally, a plurality of process technologies are currently practiced, wherein, for logic circuitry, such as microprocessors, storage chips and the like, CMOS technology is presently the most promising approach due to the superior characteristics in view of operating speed, manufacturing costs and/or power consumption. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed in and on an appropriate crystalline semiconductor material, wherein currently the vast majority of logic circuitry is fabricated on the basis of silicon. Typically, a MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed at an interface of highly doped drain and source regions with a channel region disposed between the drain region and the source region, wherein the channel region is at least partially inversely doped with respect to the drain and source regions.
The conductivity of the channel region (which represents an essential device criterion, as the reduced current drive capability of scaled devices has to be, at least partially, compensated for by an increased conductivity) is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends on the dopant concentration, the mobility of the charge carriers and, for a given dimension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length.
In addition to the conductivity, the transistor performance is also significantly influenced by its capability of rapidly creating a conductive channel in the channel region upon application of a specified control voltage to the gate electrode, since usually the transistors are operated in a switched mode requiring a fast transition from the transistor on-state to the transistor off-state and vice versa.
Moreover, other aspects also have to be taken into consideration when designing a transistor of a high performance circuit. For instance, static and dynamic leakage currents may significantly affect the overall performance of an integrated circuit, as the achievable amount of heat dissipation that is required for transistor architectures producing high dynamic and/or static leakage currents may restrict the maximum practical operating frequency.
With reference to FIG. 1, a typical transistor architecture of a field effect transistor element will now be described in more detail in order to more clearly explain some of the problems encountered in currently used transistor designs. In FIG. 1, a transistor element 100 comprises a substrate 101, which may represent a bulk semiconductor substrate such as a silicon substrate, or any other appropriate substrate having formed thereon a crystalline semiconductor layer, which may typically be formed on the basis of silicon for logic circuitry. Thus, the substrate 101 is to be considered as a substrate having formed thereon a substantially crystalline semiconductor region 102, in which are formed a drain region 104 including a so-called extension region 104e. Similarly, a source region 103 is formed in the crystalline region 102 and includes an extension region 103e. The area disposed between the extension regions 103e and 104e is referred to as a channel region 105, since here typically a conductive channel is created during the on-state of the transistor 100, as will described later on.
Located above the channel region 105 is a gate electrode structure 106 that includes a gate electrode 107 and sidewall spacers 108, 112. Moreover, a gate insulation layer 109 is provided between the gate electrode 107 and the semiconductor region 102 to electrically insulate the gate electrode 107 from any conductive regions within the crystalline semiconductor region 102. Regarding the design and material composition of the gate electrode structure 106, it is to be noted that in principle the gate electrode 107 may be considered as a conductive line, the “width” dimension of which is referred to as a gate length 107a, whereas the “length” of the line, extending in a direction perpendicular to the drawing plane, is referred to as the gate width (not shown in FIG. 1). The gate electrode 107 may be comprised of any appropriate material and is typically formed in advanced silicon-based integrated circuits of heavily doped polysilicon in combination with a highly conductive metal silicide, such as nickel silicide, cobalt silicide and the like. However, depending on the process strategy and the design criteria, other materials, such as metals, may be used. Frequently, the gate electrode structure 106 comprises the sidewall spacers 108, 112 which may, depending on process strategies, include one or more individual spacer elements and liners, wherein, for convenience, merely one offset spacer 112, for instance comprised of silicon dioxide, and one spacer 108, for instance comprised of silicon nitride, is shown.
The gate insulation layer 109 may be comprised of any appropriate insulating material such as silicon dioxide, silicon nitride and/or high-k materials to provide a required electrical insulation while maintaining a high capacitive coupling to the channel region 105. Hence, for well approved silicon dioxide based gate insulation layers, a thickness of the gate insulation layer 109 is on the order of a few nanometers, for example 2 nm and less, thereby causing moderately high static leakage currents, which may amount to approximately 30% or even more of the overall electrical losses of advanced transistor elements. Other transistor characteristics, such as switching losses and the like, will be explained later on when a typical process flow for forming the transistor 100 is discussed.
During the manufacturing process, the substrate 101 is treated to form the semiconductor region 102 with high crystalline quality, which may be achieved by epitaxial growth and the like. Thereafter, photolithography, etch and deposition processes may be performed to define the dimensions of the semiconductor region 102 by providing appropriate isolation structures (not shown). Thereafter, implantation sequences may be carried out to position one or more dopants within the crystalline semiconductor region 102 to thereby form a specified vertical dopant profile (not shown) within the region 102, which may finally result in a specified vertical dopant profile in the channel region 105.
Next, material layers for the gate insulation layer 109 and the gate electrode 107 may be formed, for instance by advanced oxidation and/or deposition techniques for the gate insulation material and by advanced low pressure chemical vapor deposition (LPCVD) for a polycrystalline silicon layer as a gate electrode material. Thereafter, highly sophisticated photolithography and etch techniques may be employed to pattern the gate electrode material and the gate insulation layer material to form the gate electrode 107 and the gate insulation layer 109 on the basis of the design gate length 107a. The gate electrode 107 may be etched by a two step (anisotropic/isotropic) etch process, wherein the polycrystalline silicon layer is predominantly anisotropically etched but a thin sub-layer (not shown) of a few nanometers is finally isotropically etched to reduce damage of the gate insulation layer 109 and of the underlying silicon regions typically caused by anisotropic etch processes.
Thereafter, complex implantation cycles may be performed to create the drain and source regions 103, 104 and the corresponding extensions 103e, 104e, wherein the gate electrode 107, partially in combination with the sidewall spacers 108, 112, acts as an implantation mask. For example, according to one strategy, a so-called pre-amorphization implantation may be carried out, during which a heavy ion species, such as xenon ions and the like, may be implanted into the crystalline semiconductor region 102 to substantially completely destroy the crystalline lattice to a specified depth, which may help in reducing any channeling effects during subsequent implantation processes. During the pre-amorphization implantation, the ion beam may be tilted with respect to a direction 110 perpendicular to the substrate 101 so as to also amorphize an area of the region 102 corresponding to the extension regions 103e, 104e. 
Thereafter, a so-called halo implantation may be performed in which an ion species is introduced that represents the same conductivity type as is already present in the channel region 105 to enhance the dopant concentration of this ion species within specific halo regions, which are indicated as 111. Similarly to the pre-amorphization implantation, the halo implantation may be performed with respective tilt angles, such as α and −α, to form the halo regions 111 at the drain side and the source side. Subsequently, a further implantation may be performed with an ion species having the opposite conductivity type with respect to the halo implantation to form the source extension 103e and the drain extension 104e, wherein an offset spacer 112 may be formed on sidewalls of the gate electrode 107 prior to the implantation. Thereafter, the sidewall spacer 108 may be formed and may be used in a subsequent implantation process as an implantation mask to form the deep and heavily doped drain and source regions 104, 103.
Thereafter, the transistor element 100 may be annealed to activate the dopant introduced by the preceding implantation sequences, i.e., to initiate a diffusion to place the dopants at lattice sites while substantially re-crystallizing those portions of the region 102 that were damaged by the pre-amorphization and the subsequent implantation processes. During this anneal cycle, thermally induced diffusion of the dopants occurs in accordance with the respective concentration gradient of the dopant species under consideration, thereby substantially determining the finally obtained size and characteristics of the drain and source regions 104, 103 and the corresponding extension regions 104e, 103e, as well as the characteristics of PN junctions 103p and 104p defined as an interface area between the halo implantation region 111 and the respective drain or source region 104, 103. During the implantation cycles and/or during the subsequent anneal cycle, a certain amount of overlap, referred to as overlap regions 103o and 104o, is created, which also significantly affects the transistor behavior. Thereafter, the manufacturing process may be continued with the formation of metal silicide regions in the drain and source regions 104, 103 and in the gate electrode 107 followed by the formation of an interlayer dielectric and respective contacts to the drain and source regions 104, 103 and the gate electrode 107. For convenience, these components are not shown in FIG. 1.
During operation, typically a supply voltage is applied to the drain region 104 and the source region 103, for example 2-5 volts for typical CPUs, while a corresponding control voltage is applied to the gate electrode 107 to define the status of the channel region 105. For the following discussion, the transistor 100 is considered to represent an N-channel enhancement type transistor in which the channel region 105 is P-doped and the drain and source regions 104, 103 and the corresponding extensions 104e, 103e are heavily N-doped. For a P-channel enhancement type transistor, the type of charge carriers involved and the conductivity type of the dopants may be inverted. Also, the following explanations in principle apply to depletion type transistors. Hence, upon application of a control voltage to the gate electrode 107 below a specific threshold voltage, which is determined by, among other things, the vertical dopant profile within the channel region 105, the transistor 100 is in the off-state, that is the PN junction 104p is inversely biased and hence a current from the source region 103 through the channel region 105 to the drain region 104 is substantially suppressed. However, during the off-state, the high electrical field prevailing at the overlap 104o may lead to tunnel currents into the gate electrode 107, especially when the gate insulation layer 109 is moderately thin, as is the case in sophisticated transistor devices. These currents may be considered as static leakage currents. Moreover, the overlap region 104o in combination with the overlying gate electrode 107 and the gate insulation layer 109 forms a capacitor, which has to be charged and discharged when operating the transistor 100 in a switched mode.
During application of a control voltage exceeding the threshold voltage, a conductive channel is formed in the channel region 105 originating from the source-side extension region 103e and terminating at the drain-side extension region 104e. For building up of the conductive channel, in the present case created by electrons, the overlap region 103o, as well as the relatively steep concentration gradient of the PN junction 103p, created by the increased dopant concentration of the halo region 111 is advantageous in obtaining a high on-current. Contrary thereto, the steep concentration gradient at the PN junction 104p may lead to enhanced currents into the substrate 101, that is, in lower-lying crystalline areas of the region 102, which may finally be drained off by a corresponding body contact, so that the dynamic leakage currents may also increase with an increase of the on-current. Moreover, during the building up of the conductive channel, the parasitic capacitances caused by the overlaps 104o, 103o may require high currents for recharging the parasitic capacitor and may delay the start of the on-state, thereby degrading the raise and fall times during the switching operation. In typical applications such as, for example, CMOS applications, the parasitic, so-called miller source capacitance, has to be discharged or loaded in each switching operation, whereas concurrently the miller drain capacitance has to be discharged and recharged with the opposite polarity in each switching operation. Thus, in conventional (symmetric) CMOS transistors, the drain miller capacitance requires twice the charge alteration of the source capacitance for each switching operation.
As can be seen from the above discussion, in addition to the overall geometric configuration of the transistor 100, such as transistor length and width, as well as material compositions, dopant concentrations and the like, also the lateral and vertical dopant profiling within the semiconductor region 102 significantly affects the finally obtained transistor performance. Due to the ongoing scaling of transistor elements, resulting in continuously increased operating speeds, a corresponding design of the drain and source architecture is important so as to not unduly offset any performance advantages gained by reducing the feature sizes owing to the increased static and dynamic losses and parasitic capacitances.
In view of the above situation, there exists a need for an improved technique that may maintain a high degree of compatibility with the conventional process flow and simultaneously enable improved drain and source designs so as to obtain an increased overall performance of highly scaled transistor devices.